Embodiments of the inventive subject matter generally relate to the field of circuit design, and, more particularly, to electronic design automation (EDA) tools to perform verification of asynchronous clock domain crossings.
EDA tools are used to evaluate chip designs prior to fabrication. The EDA process broadly consists of two steps. The first step is a check of the register transfer level (RTL) design logic. The second step is a creation of a physical circuit design from the RTL design. The first step, checking the design logic, can be referred to as RTL design checking. In RTL design checking, a language such as VHDL (VHSIC Hardware Description Language) or Verilog can be used to describe and model the logical behavior of a circuit. In some cases, a circuit design can be stored as a graph, the edges of which correspond to wires and the nodes of which correspond to circuit components. These edges can be referred to as nets, and the set of all elements that comprise the graph can be referred to as a netlist. RTL design checking itself can be decomposed into two steps. The first step is static checking and the second step is verification, which can also be referred to as dynamic checking. In static checking, the structure of the design is analyzed without simulating the behavior of the design. Conversely, in verification, the design is simulated by applying test patterns or stimuli to the inputs of the design to identify possible errors. Verification may also consist of a mathematical analysis of the state space of the design, known as formal verification or model checking, which attempts to perform the equivalent of applying all possible stimuli to the inputs of the design. Verification can be an expensive process for a complex chip or system on a chip. Verification can also be inconclusive, since it is often infeasible to apply all possible test patterns to the inputs of a complex design, or analyze its complete state space.
Chips and systems on chips continue to increase in complexity, comprising many systems and sub-systems. These systems and sub-systems might comprise multiple clock domains. A clock domain is a set of sequential logic elements, such as transparent latches and flip-flops, and combinational logic associated with these sequential logic elements that are clocked by a common clock or by clocks having common frequency and a fixed phase relationship. A clock signal causes a change in the state of sequential logic, such as a flip-flop or transparent latch. A clock domain crossing is a path from a sequential logic element or other source of state transitions in a design in a first clock domain to a sequential element in a second clock domain. The clock in the first domain may operate asynchronously with respect to the second clock domain. In such cases, when a data signal path crosses from the first clock domain to the second clock domain, the crossing is referred to as an asynchronous clock domain crossing.
Asynchronous clock domain crossings can be sources of error in chip design. Among the errors that can be propagated at asynchronous clock domain crossings are glitches and metastability. In general, a glitch occurs due to delays in inputs to a circuit component, in the delay inherent in a circuit component changing its output to reflect changes to its input, or both. For example, consider a first input and a second input to an AND gate. Assume that the first input at time t=1 is expected to transition to a 1 and the second input at time t=1 is expected to transition to a 0. However, if the second input is delayed, such that at time t=1, the second input is a 1 rather than a 0, then the output of the AND gate will be a 1 rather than the anticipated 0. Metastability occurs when a signal exists in an indeterminate state between a 0 and 1. This indeterminateness eventually is typically resolved over a period of time such that the probability of a signal remaining in an indeterminate state falls exponentially as a function of time.